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Nanoelectronic Computing

Nanoelectronic computing involves the design and analysis of nanometer-level architectures realized with semiconductor and molecular electronic technologies. Key characteristics of such architectures are regularity and randomness. Regular structures are employed but each has some random element reflective of the small dimensions involved. The crossbar, which is being investigated for use in memories and PLAs, is one such regular structure. Randomness arises in the addressing of nanowires (NWs) with a small number of meso-scale wires.

High fault rates will be an important feature of nanoelectronic computing. Computing will be done in an environment in which large reliable CMOS elements are combined with small unreliable nanolevel elements to achieve high chip density and high reliability.

Project status: Active

Project Home Page: http://www.cs.brown.edu/people/jes/nano.html

Funding

NIRT: Technologies, Architectures and Performance Analysis for Nanoelectronics, National Science Foundation, $1,300,000, 2004 - 2008

NIRT: Technologies, Architectures and Performance Analysis for Nanoelectronics (supplement), National Science Foundation, $19,995, 2005

Publications

Savage, J. E., Rachlin, E., DeHon, A., Lieber, C. M., and Wu, Y. Radial Addressing of Nanowires. ACM Journal on Emerging Technologies in Computing Systems 2, 2 (2006), 129-154. [ pdf ]

Rachlin, E., Savage, J. E., and Gojman, B. Analysis of a Mask-Based Decoder. In Procs. Annual Symposium on VLSI (May 2005), IEEE Computer Society, pp. 6-13. [ pdf ]

Gojman, B., Rachlin, E., and Savage, J. E. Evaluation of Design Strategies for Stochastically Assembled Nanoarray Memories. ACM Journal on Emerging Technologies in Computing Systems 1, 2 (Jul 2005), 73-108. [ pdf ]

Gottlieb, L.-A., Savage, J. E., and Yerukhimovich, A. Efficient Data Storage in Large Nanoarrays. Theory of Computing Systems 38, 4 (Jul 2005), 503-536. [ pdf ]

Gojman, B., Rachlin, E., and Savage, J. E. Decoding of Stochastically Assembled Nanoarrays. In Procs. Int. Symposium on VLSI (Feb 2004), pp. 11-18. [ pdf ]

DeHon, A., Lincoln, P., and Savage, J. E. Stochastic Assembly of Sublithographic Nanoscale Interfaces. IEEE Transactions on Nanotechnology 2, 3 (Sep 2003), 165-174. [ pdf ]

DeHon, A., Lieber, C., Lincoln, P., and Savage, J. E. Sub-lithographic semiconductor computing systems. In Procs. Hot Chips Conf. (Hot Chips 15) (Aug 2003), Stanford University. [ pdf ]